TechVault
RP2040
Raspberry Pi RP2040 is a microcontroller designed by Raspberry Pi. It brings Raspberry Pi’s signature values of high performance, low cost, and ease of use to the microcontroller space.
Description
Two symmetrical, fast CPU cores
Two Arm Cortex-M0+ cores, clocked at 133MHz, provide ample integer performance. Use one core to run application code, and the other to supervise hardware; or run application code on both cores, using either our C SDK, MicroPython, or with FreeRTOS SMP.
Large RAM capacity
264kB of RAM means you can concentrate on implementing features, not optimising your application for size as you would need to do with a typical microcontroller in this class. A fully connected switch connects both Arm cores and the DMA engines to six independent RAM banks, so you can squeeze every last drop of performance out of the system. It supports up to 16MB of off-chip flash, via a dedicated QSPI bus. This means you can tailor your board to customer requirements, or to any flash memory that has availability.
Flexible I/O
RP2040’s unique feature is Programmable I/O (PIO). PIO is programmable in the same sense as a processor is programmable: it enables software implementations of protocols without having to resort to bit-banging the implementation, and without affecting either of the two main CPU cores, giving the user enormous flexibility.
There are two PIO blocks with four state machines each, which can independently execute sequential programs to manipulate GPIO pins and transfer data bi-directionally; all eight state machines have independent, simultaneous access to any GPIO. Unlike a general-purpose processor, PIO state machines are highly specialised for input and output, with a focus on determinism, precise timing, and close integration with fixed-function hardware.
The flexibility afforded by PIO allows designers to emulate legacy interfaces from other devices, making it simple to replace existing microcontrollers in designs.
Features
- Dual ARM Cortex-M0+ @ 133MHz
- 264kB on-chip SRAM in six independent banks
- Support for up to 16MB of off-chip Flash memory via dedicated QSPI bus
- DMA controller
- Fully-connected AHB crossbar
- Interpolator and integer divider peripherals
- On-chip programmable LDO to generate core voltage
- 2 on-chip PLLs to generate USB and core clocks
- 30 GPIO pins, 4 of which can be used as analogue inputs
- Peripherals
- 2 UARTs
- 2 SPI controllers
- 2 I2C controllers
- 16 PWM channels
- USB 1.1 controller and PHY, with host and device support
- 8 PIO state machines
Specifications
- Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz
- 264kB on-chip SRAM
- 2 × UART, 2 × SPI controllers, 2 × I2C controllers, 16 × PWM channels
- 1 × USB 1.1 controller and PHY, with host and device support
- 8 × Programmable I/O (PIO) state machines for custom peripheral support
- Supported input power 1.8–5.5V DC
- Operating temperature -40°C to +85°C
- Drag-and-drop programming using mass storage over USB
- Low-power sleep and dormant modes
- Accurate on-chip clock
- Temperature sensor
- Accelerated integer and floating-point libraries on-chip